Impact of Random Telegraph Noise on CMOS Logic Delay Uncertainty

Logic Delay Uncertainty Takashi Matsumoto Department of Communications and Computer Engineering Kyoto University, Kyoto, Japan Email: [email protected] Kazutoshi Kobayashi Department of Electronics Kyoto Institute of Technology, Kyoto, Japan Hidetoshi Onodera Department of Communications and Computer Engineering Kyoto University, Kyoto, Japan Abstract—Statistical nature of RTN-induced delay fluctuation is described by measuring 2,520 ROs fabricated in a commercial 40 nm CMOS technology. Small number of samples have a large RTN-induced delay fluctuation. RTN-induced delay fluctuation becomes as much as 10.4% of nominal oscillation frequency under low supply voltage (0.65V). By slightly increasing the transistor size, more than 50% reduction of frequency uncertainty can be achieved under 0.75V operation. Circuit designers can change various parameters such as operating voltage, transistor size, logic stage number, logic gate type, and substrate bias. The impact of the parameters that can be changed by circuit designers is clarified in view of RTN-induced CMOS logic delay uncertainty.